Designing the Power Stage Behind FOC

Hands-on · Electronics · ~23 min read

Field-oriented control is usually taught from the software side: Clarke, Park, PI current loops, inverse transforms, SVPWM, repeat. That is the clean part.

The less clean part is the board that has to turn voltage commands into real phase current. A real FOC inverter has MOSFETs with finite gate charge, body diodes, parasitic inductance, shunts that heat up, ADCs that sample at the wrong instant, and layout loops that turn nanoseconds into volts of ringing.

When the power stage is wrong, the software does not fail politely. The symptoms look like bad tuning: audible hiss, current ripple, random over-current faults, phase-current offsets, velocity ripple at low speed, one direction behaving worse than the other, or a current loop that is stable on the bench and unstable in the robot.

This article is the hardware sequel to the FOC controller article. The goal is not to design a universal inverter. The goal is to show the checks that decide whether an FOC power stage is ready for a robot.

1. What the power stage must guarantee

FOC assumes the controller can request a voltage vector and then measure phase current that corresponds to the result. The inverter has to make that assumption true enough.

A practical FOC power stage has to do five things:

• Switch the DC bus into three phase voltages without shoot-through.
• Charge and discharge MOSFET gates fast enough, but not so fast that layout parasitics dominate.
• Measure at least two phase currents in a quiet and repeatable sampling window.
• Keep power-loop, gate-loop, and measurement-loop currents out of each other.
• Shut down in hardware when current, voltage, temperature, or driver state becomes unsafe.

If any one of those is weak, the current controller will spend its life fighting hardware errors.

2. The actual electronics: one inverter leg

The schematic excerpt below is the hardware anchor for the rest of the article. It is one real Phase U leg: the high-side MOSFET, low-side MOSFET, gate components, low-side shunt, and current-sense amplifier that turn a PWM command into a measurable motor current.

This crop is more useful than a generic half-bridge symbol because it shows the implementation details that decide whether FOC behaves:

Notice what is not visible in this crop: the upstream half-bridge driver, high-side supply, DC-link capacitors, and protection logic. Those parts still set the electrical limits of this leg. The schematic should therefore be read as a chain:

PWM -> gate driver -> GHA/GLA -> MOSFET gates -> Phase U -> R52 shunt -> U7 -> current1 ADC

The R52 shunt also makes the timing problem visible. This is a low-side leg-shunt measurement, so the ADC sample is valid only when the PWM state actually routes the phase current through that shunt. That is why current reconstruction and PWM sampling are hardware problems first and software problems second.

For a bootstrap high-side driver, the capacitor is not chosen by folklore. It must supply the charge removed from the floating high-side supply during the longest relevant on-time while keeping the driver above its UVLO threshold with margin. A useful first-pass budget is:

C_boot >= Q_total / DeltaV_boot
Q_total ~= Q_g(V_drive) + Q_driver_sw + (I_HB + I_leak_total) * t_on_max + margin

Q_g(V_drive) must come from the MOSFET curve at the actual gate-drive voltage, not from a random headline number. Q_driver_sw is the driver's own high-side switching consumption if the datasheet provides it. I_HB, leakage and diode/capacitor leakage should be checked at temperature, and DeltaV_boot must leave enough headroom above high-side UVLO after gate-drive level, diode drop and ripple are considered.

Example: if the high-side MOSFET gate charge at the chosen drive voltage is 60 nC, the driver consumes another 10 nC equivalent, leakage and high-side bias add 5 nC over the worst on-time, and you allow only 0.2 V of bootstrap droop:

C_boot >= (60 nC + 10 nC + 5 nC) / 0.2 V = 375 nF

That points to a real capacitor value such as 470 nF or 1 uF, after checking voltage bias, temperature, package, diode recovery and driver datasheet limits. A nominal 100 nF bootstrap capacitor may work on a bench at light load and still fail when the duty cycle and temperature change.

3. MOSFET selection starts after the headline ratings

The common beginner mistake is choosing a MOSFET by voltage rating, current rating, and threshold voltage. The current rating is usually package- and heat-sink-dependent. The threshold voltage only says when the device barely begins to conduct. For a motor inverter, the real questions are:

• What is R_ds_on at the actual gate voltage?
• What is the gate charge at the intended drive voltage?
• How much switching energy does the device dissipate at the bus voltage and phase current?
• How much margin exists for ringing on the switch node?
• Can the package move heat into the PCB or heat sink?

The first-pass conduction loss for one MOSFET is:

P_cond ~= I_rms^2 * R_ds_on(T) * D

Here I_rms means RMS current through that specific MOSFET in the operating condition being checked. It is not the motor nameplate current, and it is not a generic phase-current number unless that is actually the RMS current through the device over its conduction interval. D is the fraction of time that device conducts. R_ds_on(T) is not the 25 degC datasheet number unless the board somehow runs at 25 degC:

R_ds_on(T) ~= R_ds_on_25C * k_T

For many MOSFETs, k_T at hot silicon can be around 1.4 to 1.8. That means a board that looks efficient at room temperature can lose its margin after a few minutes in an enclosure.

Design rule:

Do not size the MOSFET from V_gs(th).
Size it from R_ds_on at the real gate drive, gate charge, switching energy, and thermal path.

4. The gate driver is part of the power stage

A MOSFET gate is not a logic input. It is a charge bucket with a nonlinear voltage profile. The driver must source and sink charge through the gate resistor, package inductance, source inductance, and Miller region.

The average gate-drive current looks harmless:

I_gate_avg = Q_g * f_pwm

For Q_g = 60 nC and f_pwm = 40 kHz:

I_gate_avg = 60 nC * 40 kHz = 2.4 mA

That number is not the hard part. The hard part is peak current:

I_gate_peak ~= Q_sw / t_sw

If the useful switching charge is 30 nC and the desired edge is 50 ns:

I_gate_peak ~= 30 nC / 50 ns = 0.6 A

That is why a microcontroller pin is not a gate driver. It can toggle the logic command, but it cannot control a power MOSFET edge with authority.

What to check:

• Source and sink current ratings of the driver.
• Separate turn-on and turn-off gate resistors if needed.
• Miller clamp or negative gate bias for high dv/dt systems.
• Bootstrap refresh time for high-side drivers.
• UVLO behavior on both logic and gate-drive supplies.
• Propagation delay mismatch between high-side and low-side paths.

5. Dead-time prevents one failure and creates another

In a half bridge, the high-side and low-side MOSFETs must never be on at the same time. Dead-time is the intentional gap between turning one device off and the other on.

A conservative timing budget is:

t_dead >= t_prop_mismatch + t_off_slow + t_on_uncertainty + t_margin

That keeps both MOSFETs from conducting together. But excess dead-time is not free. During dead-time, the phase current continues through the body diode or synchronous path, causing voltage error and extra loss.

A useful first-order voltage error is:

V_error_avg ~= sign(i_phase) * V_drop * t_dead / T_pwm

The sign depends on the phase-current convention and which device would have been conducting. Current direction decides whether dead-time raises or lowers the effective phase voltage, so use this equation as a magnitude and sign-convention check, then verify it on the actual bridge.

For a 40 kHz PWM period (T_pwm = 25 us), t_dead = 500 ns, and a diode/synchronous drop around 0.8 V:

V_error_avg ~= 0.8 V * 0.5 us / 25 us = 16 mV

That looks small until low-speed FOC asks for only a few hundred millivolts of phase voltage. Then dead-time distortion becomes torque ripple.

Design rule:

Use enough dead-time to cover real turn-off uncertainty.
Then reduce the remaining voltage error in firmware or gate timing, not by pretending it is zero.

6. Switching loss is voltage-current overlap

Conduction loss is easy to estimate. Switching loss is where the board starts arguing with the datasheet. During a switching edge, drain-source voltage and current overlap. The area under that overlap is energy.

The first-order estimate for one transition is:

E_sw ~= 0.5 * V_bus * I_phase * t_overlap

For both turn-on and turn-off:

P_sw ~= f_pwm * (E_on + E_off)

If V_bus = 48 V, I_phase = 20 A, and the effective overlap is 80 ns per edge:

E_edge ~= 0.5 * 48 * 20 * 80 ns = 38.4 uJ
P_sw_pair ~= 40 kHz * 2 * 38.4 uJ = 3.1 W

That is for one switching path under one operating point. Repeat this per switching device and operating point: bus voltage, phase current, temperature, edge rate and modulation all change the result. Then add conduction, diode, gate-drive, shunt, and copper losses.

The tradeoff:

• Faster edges reduce switching overlap.
• Faster edges increase ringing, EMI, false current trips, and stress.
• Slower edges are quieter but hotter.

The gate resistor is not a magic EMI knob. It is a thermal, timing, and noise tradeoff.

7. Current sensing: the ADC only sees what the layout allows

FOC needs phase current. Most systems measure two currents and infer the third:

i_a + i_b + i_c = 0
i_c = -(i_a + i_b)

That identity only helps if the two measured currents are real, sampled at the same effective instant, and not polluted by switching noise.

The shunt equation is simple:

V_shunt = I_phase * R_shunt

The power loss is just as simple:

P_shunt = I_rms^2 * R_shunt

The ADC sees the amplified shunt voltage:

ADC_counts ~= ((V_offset + V_shunt * G) / V_ref) * (2^N - 1)

Example: a 1 mOhm shunt at 30 A produces 30 mV. With gain 20, the ADC input sees 600 mV above the offset baseline. On a 3.3 V, 12-bit ADC, the dynamic contribution is:

Delta_counts ~= 0.6 / 3.3 * 4095 = 745 counts

That is usable. But the same shunt dissipates:

P_shunt = 30^2 * 0.001 = 0.9 W

So the shunt is not only a sensor. It is a heater, a layout element, and often part of the fault path.

8. The sampling window is part of PWM design

Before the firmware talks about i_alpha and i_beta, the PCB has to turn a few millivolts across a shunt into a voltage the ADC can trust. In Figure 2, that path is explicit: R52 creates the shunt voltage, U7 amplifies it, R64 and C37 condition the current1 signal, and the controller samples that voltage as current.

For this kind of shunt front end, treat the amplifier as an analog circuit, not as a software variable:

V_adc = (I_phase * R_shunt) * G + V_offset

Choose R_shunt and gain so the ADC has useful signal at normal current, but the amplifier does not saturate before the hardware current limit trips.

Example for a 12-bit, 3.3 V ADC:

R_shunt = 1 mOhm
G = 20
I_peak = 40 A
V_adc_peak = 40 A * 0.001 ohm * 20 = 0.8 V
counts_peak ~= 0.8 / 3.3 * 4095 = 993 counts

That leaves headroom for offset and fault margin. If the same design must detect 80 A in hardware, the comparator should use a fast analog path or the gate driver over-current input instead of waiting for the ADC conversion.

The Figure 2-style front-end checklist:

• Kelvin route the shunt pads; do not measure through the power copper.
• Put any differential RC filter at the amplifier input, not at the other end of a noisy trace.
• Keep the amplifier input common-mode range valid for the chosen sensing topology.
• Align the ADC trigger with the quiet part of the PWM period.
• Run a separate fast comparator or driver over-current input for destructive faults.

Current should be sampled when the measurement path has settled after a switching event. In center-aligned PWM, the best sample point is often near the center of a quiet region, not immediately after an edge.

The available sampling window can be approximated as:

t_window ~= T_pwm / 2 - t_dead - t_settle - t_adc

This simplified estimate assumes a usable center-aligned quiet region exists. The actual observable window changes with duty cycle, SVPWM sector, low-side shunt conduction state, blanking time, amplifier recovery and switch-node ringing.

Where:

• t_dead is the dead-time around the transition.
• t_settle is amplifier, filter, and ringing settle time.
• t_adc is acquisition and conversion time.

If T_pwm = 25 us, t_dead = 0.5 us, t_settle = 1.2 us, and t_adc = 0.4 us:

t_window ~= 12.5 us - 0.5 us - 1.2 us - 0.4 us = 10.4 us

That is comfortable. But at high modulation index or with low-side shunts, one or more phases may not have a valid measurement window. The problem is not "ADC resolution"; it is observability.

Design rule:

Choose current-sense topology and PWM strategy together.
Do not choose the shunt first and discover the sample window later.

9. Layout: the schematic is not the circuit

The fastest way to ruin a good power stage is to route it as if the schematic nets were the circuit. They are not. The current loops are the circuit.

The voltage spike from loop inductance is:

V_spike = L_loop * di/dt

With only 10 nH of stray inductance and 50 A/us:

V_spike = 10 nH * 50 A/us = 0.5 V

At 100 A/us, that is already 1 V. In real layouts, the problem is often larger because the spike rides on the source reference seen by the driver and the shunt amplifier.

That source bounce is not just a cosmetic spike on the oscilloscope. It changes the effective V_GS, can trigger false comparator or gate-driver faults, can corrupt the shunt amplifier's differential input, and can inject ground or reference error into the ADC. A bridge can look correct in the schematic and still fail because the measurement and gate-drive references move during each edge.

Layout rules that matter:

• Put the DC-link ceramic capacitors tight to the half bridge.
• Minimize the high-frequency loop: capacitor -> high-side MOSFET -> low-side MOSFET -> capacitor.
• Keep gate-driver loop area small and separate from the power loop.
• Use Kelvin source or Kelvin shunt routing for measurement and gate reference.
• Keep shunt amplifier inputs differential, short, symmetric, and away from switch nodes.
• Do not split the ground plane under fast return currents and then ask the ADC to be precise.

10. DC-link capacitance and regeneration set the bus behavior

The DC link is not just a large capacitor across the supply. It is the local current source for PWM ripple, the sink for returned motor energy, and part of the high-frequency switching loop. Ceramic or film capacitors handle the fast loop near the half bridge; bulk capacitance handles lower-frequency energy and bus stiffness. ESR, ESL, placement and ripple-current rating matter as much as the nominal capacitance.

A first-pass bus-ripple estimate is:

DeltaV_bus ~= I * DeltaT / C

If a 20 A current pulse is supported by 100 uF for 5 us:

DeltaV_bus ~= 20 A * 5 us / 100 uF = 1 V

That estimate ignores ESR step, ESL spike, capacitor DC-bias derating, temperature, ripple-current heating and the supply response, so it is only a starting point. It tells you whether the capacitance is in the right decade, not whether the bus is clean.

Regeneration is the other half of the DC-link problem. During braking or overhauling loads, the motor can return energy to the bus faster than the supply or load can absorb it. Bulk capacitance only delays the voltage rise; it is not a regeneration strategy. A real design needs one of these paths:

• A supply that can sink current.
• A braking resistor or dump path sized for the returned energy.
• An active regeneration path.
• A hardware over-voltage trip that disables PWM before the bus exceeds component ratings.

Review the DC link with the same discipline as the MOSFETs: local high-frequency capacitors at the bridge, bulk capacitance with a low-inductance path, ripple-current rating, over-voltage behavior, and scope measurements at the actual power pins.

11. Protection should not wait for firmware

Firmware can decide what to do after a fault. It should not be the first thing that notices a destructive fault.

A practical protection path includes:

• Cycle-by-cycle over-current comparator.
• Driver UVLO fault.
• Over-temperature signal or thermal model.
• DC-bus over-voltage check.
• Brake or dump path where regeneration can raise the bus.
• Hardware PWM disable input that does not depend on the main loop.
• Firmware latch and explicit recovery sequence.

The timing rule is:

t_fault_detect + t_pwm_disable < t_damage

If shoot-through or a phase short can destroy silicon in a few microseconds, a task running at 1 kHz is not a protection system. It is a historian.

12. Bring-up sequence

Do not bring up an FOC inverter by running FOC. Bring it up as a power electronics board first.

Recommended sequence:

1. Power logic only. Verify rails, driver UVLO status, fault pins and firmware-safe PWM defaults.
2. Drive gates with no bus voltage. Measure high-side and low-side gate signals at the MOSFET pins.
3. Apply a current-limited low DC bus. Use a dummy load or motor disconnected when appropriate.
4. Toggle one leg at low duty. Inspect phase node, gate ringing and driver temperature.
5. Verify dead-time on the scope at the actual gate pins.
6. Calibrate current-sense offsets with PWM disabled.
7. Enable PWM and sample current during known quiet windows.
8. Run open-loop voltage vector at low bus voltage.
9. Close the current loop with conservative limits.
10. Only then connect the full FOC stack.

The first successful spin is not proof. The first clean current waveform under load is proof.

13. Symptom table

14. Power-stage review checklist before closing the current loop

Before closing the current loop, the review should be able to answer these points without hand-waving:

• MOSFET losses are estimated per device at hot silicon, including conduction, switching, diode and gate-drive loss.
• The selected gate driver can source and sink the required peak current at the intended gate-drive voltage.
• Bootstrap capacitance, high-side UVLO margin and worst-case on-time have been checked.
• Dead-time is measured at the MOSFET pins, and its voltage error has a compensation or calibration plan.
• Current shunts, gains and ADC ranges leave margin for offset, fault current and amplifier saturation.
• ADC triggering is valid across duty cycle, modulation index and SVPWM sector, not only at one bench condition.
• The DC link has local high-frequency capacitance, bulk energy storage, ripple-current rating and a regeneration path.
• Hot-loop, gate-loop and current-sense-loop routing are intentionally separated and verified with probing.
• Source bounce, switch-node ringing and shunt spikes have been measured at full bus voltage.
• Hardware faults disable PWM without waiting for the main firmware loop.
• Bring-up proves rails, gates, current sensing, protection and thermal behavior before full FOC runs.

15. The decision

FOC software can only control the plant it can observe and actuate. The inverter is the actuator and part of the sensor.

The final rule:

FOC does not fix a noisy inverter.
FOC reveals it.

Build the power stage so the current loop sees the truth.

---

This article is based on practical power-electronics design, embedded motor-control bring-up, FOC current-loop implementation, gate-driver behavior, current-sensing practice, and PCB layout experience. Always verify MOSFET losses, driver limits, current-sense timing, protection behavior, and layout parasitics against the specific voltage, current, motor, and switching frequency in front of you.